Maintaining bit status after power failure

[ElctriclCncepts 0]

I am having a problem keeping the status of a few bits after power failure. Maybe I'm going about this all wrong, so I would like for someone to help me out if you will be so kind to do so. I am using the Omron CPM2A CPU and in the program I have a section where I have the unit monitoring the status of a few photo eyes. These eyes control the fill of several holding tanks and at power loss the valves remain close, but at powering up they open for a brief moment and then return to their original state. I used the HR data memory area for this app. and it seems to not have any effect as far as retentivity of the state of the actuators. What am I doing wrong? Could someone help or possibly leave a drawing as an example of correctly using the HR bits. Edited 21 May 2004 by ElctriclCncepts

[Jay Anthony 118]

Post us a screenshot of the troubling circuit so that we can better analyze it. Remember, you get the advantage of many eyes reviewing your problem. You're on the right track with HRs but there may be a flaw in your logic.

[ElctriclCncepts 0]

I don't know how to do the screen shot so that you guys can actually see the circuit. But what I can do for those who will understand is give a statement list. LD 0.00 TIM 001 #20 LDNOT TIM001 OUT HR0.00 LD HR0.00 OUT LD 10.00 Sorry this is the best that I can do. This circuit consist of a external input 0.00 that if it is found to be true it triggers a timer. The timer then would open a rung in which that HR0.00 is the out. HR0.00 is also being used to manipulate the external out put with addressing of 10.00. Now it is to my understanding that the HR data memory area will retain it's values 1's or 0's even if there is a loss of power. I was led to believe that there is no reason that for the actuators to open if at power loss when the value at HR area 0.00 is not true. Edited 21 May 2004 by ElctriclCncepts

[KinK 0]

Ok I think that I may have an Idea of your problem. the HR area will maintain its logic but the logic controling that HR bit will not..... so when the power comes back on the timer is reset and that will reset HR0.00. you need to latch HR in some how so that the logic controling it does not affect it when the power goes out. you can make a screen shot using the print screen button then go to Paint and paste. Edited 21 May 2004 by KinK

[Jay Anthony 118]

KinK is right. HRs are data retentive, but your logic isn't. Therefore, you need to latch HR00.00 so that it will retain the latch through a power down condition. Give the below circuit a try. LD 0.00 TIM 001 #20 LD NOT TIM001 SET HR0.00 LD NOT 0.00 RSET HR0.00 LD HR0.00 OUT 10.00

[ElctriclCncepts 0]

I get it now, someone told me that the initial scan of the cpu would automatically acknowledge the HR's and skip anything else. Thanks a lot fellas, J in Chicago.

[Yair 2]

Instade of using Tim&HR BIT&SET&RSET You can us one CNT in negative logic CNT's are data retentive, But timers are not. see jpg

[Jay Anthony 118]

Yair: I thought about that one, but he was centering on HRs so I stayed on that track. Thanks for the inverter pdfs. This is an Omron Europe product. We're just beginning to hear about it. ElctriclCncepts: Just figured out your avitar. Kewl!

[ElctriclCncepts 0]

Thx, I really enjoy using the Omron software. I have a friend who has worked with you on a project here in Chicago Jay. I was talking to him about some things and mentioned this site and your name. He told me to say hello to you for him. He's out of Kiser controls here in Burr Ridge. Mr. Frank Serritella controls engineer. But you guys keep the ideas coming I'm always interested in gainning an advantage. Thx, again for the counters info I'm exploring all avenues. I used the Set and RSET w/ a W bit and latch to manipulate the circuit to get the effect I wanted. You guys are amazing here. Edited 24 May 2004 by ElctriclCncepts