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Showing results for tags 'qj61bt11n'.
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Hello, I have a project where i will be adding a new R04CPU to an existing CCLink network via RJ61BT11. The existing network has 5 stations and the Master module is a QJ61BT11N. I am new to CCLink and have tried learning more through the manuals but i still have unanswered questions i cant seem to find answers to. By adding this RJ61BT11 to the existing network as station 6, I will have to configure the settings on the RO4CPU for the RJ61BT11, aswell as on the QCPU for the master QJ61BT11N. Is this correct? By adding this to the network using the CCLink Configuration Tool in GXWorks2, I get the error (The Refresh Device settings are overlapping). Its referring to the Remote Inputs/Ouputs and the Remote Registers. How do I know what to set these ranges to? If these ranges change, Will this effect the current program that is referencing certain inputs/outputs and addresses? Or will it only add to the end of the existing range, therefore leaving the addresses used intact? Im going to attach an image of the Current, Existing settings (No implementation of the RJ61BT11) that are working on the machine. My goal is to implement the new R04 PLC to handle a vision application and transfer data between the main machine (QPLC), such as recipe data, and vision results. Any help would be greatly appreciated.
Hello, I would be adding two 32bit DI modules in existing CC-link network in one of my projects (on Q06HCPU). I am trying to figure out the X & Y address areas in CPU for these additional stations. Currently the network has 27 modules, 0-33 stations. I read the CC-link master user's manual (SH_NA_080394-M) but few things are not clear yet. What is the purpose of Srart XY or Start I/O No.in PLC parameter (0080 for the CC-link master)? Is it to identify and fix the location of the CC-link master? In other words, nothing to do with device memory for Remote Input (RX) and outputs (RY)?In CC-Link network parameters I have following setting - RX : X1000, RY : Y1000, RWr : D4000, RWw : D4200. X & Y defines device memory in CPU, 32 bits per station for the Digital IO (for 16 bit output first 16 bits are used, next 16 bits are unusable, correct?) but not sure what is the use of RWr and RWw. Also, there are 4 ch. Analog inputs that takes one station and 8 Ch. Thermocouple modules that take 4 stations.With above information how would I know where my digital IO addressing should start for additional stations 34 & 35?I have tried to glance through Q-Cpu programming manual and few others but its not clear to me. And as usual I am running out of time. I would appreciate any hints, suggestion of documents and answers of my questions. Thanks B