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Guest Guest_Sergei troizky

Interrupt nesting in FX1N

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Being recently involved in debugging of FX1N program with massive interrupts, I have performed some simple programming tests to clarify for myself the FX1N behavior in sense of interrupts nesting and lost interrupts. Some of the results are unexpected. Test 1. High-speed pulse output Y0 is connected directly to the high-speed input with interrupt assigned. Y0 generates known number of pulses and the test is performed with different Y0 frequencies. A data register increment is performed in the interrupt in order to monitor the number of interrupt executions. Test result: after some frequency of Y0, some of the interrupts are lost. This is an expected and obvious result. Note: there is no any indication of lost interrupts in the PLC devices. Test 2. Same as test 1, but Y0 is connected to two high-speed inputs, resulting in simultaneous request of two interrupts. A data register increment is performed in each interrupt in order to monitor the number of each interrupt executions. Test result: after some frequency of Y0 some of the lower priority interrupts are lost, while the interrupt with higher priority is still performed on each pulse. Conclusion: after simultaneous request an interrupt with lower priority waits to be executed, but not in "first come first served" line. If another higher priority interrupt occurs, this lower priority interrupt waits again and may be lost. This is an expected, but not an obvious result. Test 3. Same as test 1, but in the interrupt body another output (Y1) is set, refreshed, reset and refreshed again. In another words, interrupt generates short Y1 pulse strictly during its execution. Y1 is connected to another high-speed input with another interrupt assigned. This second interrupt increments two registers: one same as in the previous tests and another increment is under Y1 condition in order to indicate the second interrupt execution during Y1 pulse (meaning interrupt nesting). The result: nesting never detected. Both interrupts increment registers, but the conditional increment in the second interrupt is never performed. This means the second interrupt still waiting instead of being nested !? Test 3 was performed with and without enabling interrupts within the interrupts bodies. Also the interrupt priorities were exchanged. All with the same result. This is totally unexpected. Can anybody explain me this ?

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