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neech

RSLogix500 Ladder Problem

7 posts in this topic

Ok, so I have 22 bits that I need to monitor the status of; all in separate words. Each change of state (on each bit) I need to trigger a timer and have the timer done to completion. I'd like to have the timer reset if a bit changes state during timing. I'd like to keep it to one timer.

I'd like to keep things as simple as possible so the less rungs / branches the better. Any help?

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Not sure exactly what you're looking for...


So you have a bunch of bits.

Do you simply want to know the elapsed time since any bit changed state? Either going on-off or off-on?

It will be simple if they're in one word, which is easy to do if it's 5000 platform. First copy the bits into a DINT address:

XIC Bit0 OTE Word.0

XIC Bit1 OTE Word.1

etc.

Then simply do a compare. If the word is not equal to its predecessor, reset the timer and move the word into its predecessor.

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Since you mentioned RSLogix 500 I'll stick with N registers. Gather the bits in to two N registers (lets say N7:0 and N7:1) in the manner suggested by Joe E. In RSLogix500 this would look like XIC Bit0 N7:0/0 etc    (After N7:0/15 you would need to switch to N7:1/0  etc) Make sure to start out somewhere with a CLR of these two N registers. The movement of the bits into tthe N registers would have to happen every scan.

For this you will also need two other N registers. Lets say N7:2 and N7:3   You can CLR these also if you wish but the only possible problem would be on the very first scan.

It sounds like you want the timer to be on if any of these 22 are on. You want it to reset if any bit changes state. So the rung to the timer enable would look like:

NEQ N7:0 0      EQU N7:0 N7:2   EQU N7:1 N7:3 ------------ Timer

NEQ N7:1 0

(Note - two NEQs are in parallel)

and another rung to store the bits to make the transition check possible:

------------  MOV N7:0 N7:2   and on a branch in parallel with this  MOV N7:1 N7:3

Edited by b_carlton
Parallel NEQ instrucctions

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Thanks guys, that worked (almost) perfectly. The only issue is when the last bit goes low, the timer doesn't start. So, when N7:0 and N7:1 both go to zero...maybe I can figure it out from here though. I appreciate your help.

HERE IS THE CODE:

SOR BST CLR N7:0 NXB CLR N7:1 BND EOR  SOR XIC B3:0/0 OTE N7:0/0 EOR  SOR XIC B3:1/0 OTE N7:0/1 EOR  SOR XIC B3:2/0 OTE N7:0/2 EOR  SOR XIC B3:3/0 OTE N7:0/3 EOR  SOR XIC B3:4/0 OTE N7:0/4 EOR  SOR XIC B3:5/0 OTE N7:0/5 EOR  SOR XIC B3:6/0 OTE N7:1/0 EOR  SOR XIC B3:7/0 OTE N7:1/1 EOR  SOR XIC B3:8/0 OTE N7:1/2 EOR  SOR XIC B3:9/0 OTE N7:1/3 EOR  SOR BST NEQ N7:0 0 NXB NEQ N7:1 0 BND EQU N7:0 N7:2 EQU N7:1 N7:3 TON T4:0 1.0 10 10 EOR  SOR BST MOV N7:0 N7:2 NXB MOV N7:1 N7:3 BND EOR  

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NEQ N7:0 0                                     EQU N7:0 N7:2   EQU N7:1 N7:3 ------------ Timer

NEQ N7:1 0

EQU N7:0 0      EQU N7:1 0

RAW CODE FOR THAT RUNG FIXING THE ISSUE

 BST NEQ N7:0 0 NXB NEQ N7:1 0 NXB EQU N7:0 0 EQU N7:1 0 BND EQU N7:0 N7:2 EQU N7:1 N7:3 TON T4:0 1.0 10 10

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You have logically thown out the need for the parallel NEQ and EQU tests on N7:0 and N7:1. Just leave the tests for EQU N7:0 N7:2 and EQU N7:1 N7:3

Edited by b_carlton

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You are right. I tested it and it is working. Thanks again for your help!

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