Are these branches normal or having some difference in SCAN time?

[Ganesh Patil 0]

In old program of a I have found some parallel branches at output please conform mi these are normal parallel branch or having some difference in SCAN time or else since it is not taken direct parallel in each other. See the snap & please reply

[Filthy McNasty 28]

Those in the diagram are mostly nested branches and a couple of parallel branches.

That rung will take longer to scan than if the outputs would have been made parallel branches instead of nested branches.

Scan time can be further reduced by putting the outputs in series. Another advantage of putting the outputs in series

is that you won't crowd out the screen with that rung. It may allow 2 or 3 adjacent rungs to be displayed thus minimizing the need to scroll up/down as much.

 

Edited 12 Dec 2016 by Filthy McNasty
Accuracy

[PLCMentor.com 60]

Interesting.  Other than being harder to read, I had not heard that extended branches and branches as you show would cause additional scan time.  I guess if you were to look at it in mnemonic view you would see additional commands that the processor has to scan so it does make sense.  I cant imagine that you would be talking about anything significant.  Maybe microseconds added to the scan?  I would be more concerned about all of the unlatch instructions I see.  With that many unlatches it would indicate that the program has latches and unlatches throughout.  That gets ugly for troubleshooting and modifications.

[Gerry 13]

I wonder if there's any difference in scan time using individual BOOL tags vs. aliasing them to bits in a DINT.

It's definitely wasteful of memory.

[Filthy McNasty 28]

On 12/12/2016 at 5:27 PM, Gerry said:

I wonder if there's any difference in scan time using individual BOOL tags vs. aliasing them to bits in a DINT.

It's definitely wasteful of memory.

I believe the physical location of the memory used for the base tag & any aliases to it, is determined during the compile phase. If it is, there is no resolution needed during the scan so I don't think scan time would be affected.

The question of individual bits vs. alias to DINT members comes down to what you're using the BOOL's for. If it is total isolation (such as ONS instructions) vs. situations when you m,ay want to be able to affect more than one of the BOOLs.

While an individual BOOL does scrap the remaining 31 bits of the DINT required to allocate space for the BOOL, I don't think the memory wasted would be a big concern given how much memory are in the controllers these days.