Decypher RSLogix5000 ladder

[servant 0]

A1 Q1 B1 ---+---] [----------(L)--+------+-------------------(L)--- | | | | A3 Q2 | | A4 B2 +---] [----------(L)--+ +----]/[------------( )--- | | | A5 Q3 | +---] [----------(L)--+ | | | A6 Q4 | +---] [----------(L)--+ | | | A7 Q5 | +---] [----------(L)--+ There is nothing in the program to unlatch Q1 thru Q5. What is the execution order for this rung? I suppose if A1 goes true, then Q1 will energize, thereby energizing B1. If A1 goes false, will B1 also go false even if Q1 stays energized? Does anyone have a reference to a document that elaborates on the logic execution order, even when coils are not at the far right position?

[TimWilborne 108]

Your code didn't post clearly. Can you post a screen capture of your program or your actual program?

[Stupidav 1]

It is just like reading, from Left to Right. I am not sure why, but it is generally a good practice to have the outputs setup this way. You are better off to have one of the outputs in a brach below the other. Yes, if A1 is true, Q1 and B1, will also be true. If A1 goes false both Q1 and B1 will stay true, atleast until thier coresponding output is Unlatched, because they are (L) Latching outputs. If Q1 is unlatched, B1 will still be true, or the oppisite. If you are worried about one of the two outputs turning on before the other, don't. The execution is to read the inputs then, then the program one rung at a time from rung 0 to the last and then the physical Outputs are updated. Order of rungs can make a difference, because as the rungs are run they update the memory, which then affects any following rungs through the end.

[Gerry 13]

I had to reconstruct using a fixed font... Execution order is left to right, top to bottom. If any of A1, A3, A5, A6, A7 are true, B1 will latch along with corresponding Q1-Q5. Also, if A4 is false while any of the afore-mentioned A's is true then B2 will be true. B1 and the Q's will stay on until unlatched or cleared.

[TConnolly 13]

This is perfectly legitimate in the CLX PLC. Creating branches creates additional code when the program is compiled, so placing outputs in series actually produces a more compact code. AB teaches this method in its CLX training courses.