Search the Community

Showing results for tags 'AJ65SBTB1-32D1'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Found 1 result

  1. Hello, I would be adding two 32bit DI modules in existing CC-link network in one of my projects (on Q06HCPU). I am trying to figure out the X & Y address areas in CPU for these additional stations. Currently the network has 27 modules, 0-33 stations. I read the CC-link master user's manual (SH_NA_080394-M) but few things are not clear yet. What is the purpose of Srart XY or Start I/O PLC parameter (0080 for the CC-link master)? Is it to identify and fix the location of the CC-link master? In other words, nothing to do with device memory for Remote Input (RX) and outputs (RY)?In CC-Link network parameters I have following setting - RX : X1000, RY : Y1000, RWr : D4000, RWw : D4200. X & Y defines device memory in CPU, 32 bits per station for the Digital IO (for 16 bit output first 16 bits are used, next 16 bits are unusable, correct?) but not sure what is the use of RWr and RWw. Also, there are 4 ch. Analog inputs that takes one station and 8 Ch. Thermocouple modules that take 4 stations.With above information how would I know where my digital IO addressing should start for additional stations 34 & 35?I have tried to glance through Q-Cpu programming manual and few others but its not clear to me. And as usual I am running out of time. I would appreciate any hints, suggestion of documents and answers of my questions. Thanks B