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Joe Cody
We have a ControlLogix Quad-5 that we're connecting to a DeltaV System via a Mynah VIM module on Ethernet/IP. The data transfer can take place in one of two methods. The first is a traditional Class 3 Encapsulated DF1 connection, wherein we create SLC mappings on the CLX side and DeltaV reads and writes to the registers. The other option is a Class 1 ENBT connection where the DeltaV datasets are represented as I/O modules on the CLX. In terms of memory and processor loading on the CLX, does anyone know if there are any advantages or disadvantages to doing it one way or the other? The ENBT connection gives higher transfer speeds, but I'm strictly concerned with loading on the CLX.

Thanks in advance!
paulengr
QUOTE (Joe Cody @ Jun 25 2009, 04:15 PM) *
We have a ControlLogix Quad-5 that we're connecting to a DeltaV System via a Mynah VIM module on Ethernet/IP. The data transfer can take place in one of two methods. The first is a traditional Class 3 Encapsulated DF1 connection, wherein we create SLC mappings on the CLX side and DeltaV reads and writes to the registers. The other option is a Class 1 ENBT connection where the DeltaV datasets are represented as I/O modules on the CLX. In terms of memory and processor loading on the CLX, does anyone know if there are any advantages or disadvantages to doing it one way or the other? The ENBT connection gives higher transfer speeds, but I'm strictly concerned with loading on the CLX.

Thanks in advance!


With the class 1 method, the processor simply allocates a memory space and connections and dumps the packet (just one packet transmitted periodically) into the memory space or vice versa. It's I/O. It's designed for low overhead and latencies. This is also all handled on the I/O processor, NOT the main processor.

With the class 3 method, there are actually 2 packets for a read, and 3 packets for a write. And the processor is no doubt involved in handling this one since effectively it's the same as as CLX "MSG" command to pass data between processors using the SLC read/write methods.

Because there are two different CPU's involved though I think the only way you can get a definite answer is to try a series of experiments and see what happens. Try it with a very fast RPI (say 3-5 ms), using both methods, and monitor the CLX to see what happens.
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