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mhowasso

MicroLogix 1 Button Latch Unlatch

36 posts in this topic

It's didn't work because if B3:0/0 is off, logic will set it [XIO B3:0/0 OTL B3:0/0] then the program reach the branch [XIC B3:0/0 OTU B3:0/0] and reset B3:0/0. Double clic on the rung number to see how the program is scanned: XIC B3:0/1 ONS B3:0/2 BST XIO B3:0/0 OTL B3:0/0 NXB XIC B3:0/0 OTU B3:0/0 BND

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ok I did my homework and now I can offer to you ver3 who contain latch/unlatch thru one pushbutton and value is retain thru power cycle. Mhowasso, note that previous version work but they lose status of memory bit on power cycle. This is mean if axis is lock, it will be unlock on power up. I'm sure sure one of those version will fit to your application. I did a mistake (who can say he never make one) about power up and I'm sorry for that. For me, the best way is a simple way, without too many unclear rung and also....with comment! I prefer ver2 if you don't care about power up, if retentive is needed use ver 3 ONE BUTTON LATCH UNLATCH 3 version.RSS

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Hi SLCMAN... You are the MAN..!!! Thanks so much for your replies. I, like most, just want to learn and do things the best way the first time. I also understand that sometimes there is not a BEST way, but many ways that will work and get the job done. Thanks again for your patience with me. PS. Just curious, what is the fix for Shiner's program..??? Edited by mhowasso

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I already post a reply to this program. Look at post 26

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Just another angle, the status of the counter is retained ONE BUTTON LATCH UNLATCH 3 version.RSS Steve

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Here's the method I use most frequently, although I like the counter method as well: This one takes a couple of storage bits for the inline oneshot and the toggle interlock, but it is pretty easy to follow for the average maintenance guy, and easy to modify to allow other conditions to trigger or inhibit the toggling: Edited by OkiePC

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Thanks Okie....that toggle interlock bit is the solution to the problem with my quick attempt at a simple one rung version. I had never had to do this with AB, did it with eaton and they have an ALT function which changes state every time a leading edge hits it. makes this pretty simple.

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Hi Nephets, This worked well as written, but for my application I needed the actual Latch and Unlatch because of power cycle issues. I have become very intriged tho by the many ways of using only one input to systematically latch and unlatch the same bit. Thanks for your version. Mark

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Hi Okie, I believe you are right, this worked smooth and clean. I now think what causes me the most trouble is the differences between the behavior/requirements between the different processors (ML1200, SLC500, etc) but using the same RSLogix500. Its just the little differences in the instruction behavior that gets me. Thanks, Mark Edited by mhowasso

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ONS or OSR? I am guessing that is the source of your trouble. I just type OSR on a blank rung and see what happens. If a big block appears on the output side, I delete it and go with the ONS. It used to be that all SLCs used one and the PLC-5 used the other, but that is no longer true with the newer Micro's. Ron Beaufort has some nice posts on the subtle differences between them. If power cycling issues are a major concern, you may want to hunt for his threads on the subject for a very detailed understanding. With the OTL and OTU there should be no difference among all of a/b's offerings, but with the ONS/OSR storage bit, and how the rung-in conditions affect it, that may not always be the case during pre-scan: http://www.plctalk.n...ghlight=OSR+ONS I think this one has the most meat in it: http://www.plctalk.n...ghlight=OSR+ONS Paul Edited by OkiePC

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Hi Paul, Thanks for the info. PLC's are one of the many items that can go from fairly straight forward and somewhat simple, to complication and frustration in one scan rate..!!! Mark

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