Reset high speed counter in CP1L

[Andy_P 7]

I want to reset the PV of a high speed counter (which is configured for diff-pase, software reset) in a CP1L when an interrupt task is executed. First of all I tried turning on the HSC reset bit, but since the interrupt task only runs for one cycle, the bit does not go off again, and hence, no further resets take place. I have since used the PRV instruction to set the value to zero, and this seems to work ok. Is this the best way to do what I want, or does a 'better' way exist? (Maybe turn off the HSC reset bit in the main program perhaps?) Thanks for any opinions! Andy.

[Sergei Troizky 26]

If the HSC to be reset only in the interrupt and the encoder zero pulse not used- just connect physically the HSC reset input with the interrupt input and nothing to be done by the software (only the hardware reset enable bit to be always On). Edited 25 Feb 2008 by Sergei Troizky

[Andy_P 7]

I am unable to do that because the input is taken, and I can only reset the HSC in software. Thank you for the suggestion though. Andy.

[Sergei Troizky 26]

Well, then I would reset the bit in the cyclic task, if the interrupt cannot appear more often than once per scan. Otherwise reset it in a fast enough timer interrupt. Edited 25 Feb 2008 by Sergei Troizky

[benbrad 0]

I reset a CJ1M HSC using INI, I just preset the count to 0. This is done in an interrupt and works fine.

[Andy_P 7]

Cheers, the INI method works well. Thanks, Andy.